Considerations for the use of Application-specific integrated circuits in conjunction with Field-programmable gate arrays to efficiently calculate repetitive tasks in regards to Rosetta

Hello everyone. Lately iv been thinking about alternative computational architectures and their possible benefits and pitfall in regards to "heave lifting". my question is as fallows. would it be feasible to develop an ASIC based computer to calculate repetitive tasks such as protean folding that would faster, use less power, and be more compact ,in comparison to existing general use computers?(laptops, desktops, server units)

feel free to leave your thoughts

FPGA???
We are waiting for gpu client... :-P

---

ASIC: application-specific integrated circuit. So no way, rosetta code is still under development. And the development of such chips isn't cheap either.

That leaves us with FPGAs only. I can't say wether it's actually possible to use them for rosetta or not, but considering that rosetta is quite complex application, I could imagine, that it simply won't fit into an FPGA, since you basically have put the entire appication into hardware.

Than of course you could try to use it just as a co-processor for repetitive tasks like stated in the thread title, but than the question is if there are such tasks in Rosetta, which are repeated often enough. And the other question is, wether you can transfer the data quick enough from the CPU to the FPGA. This is often the reason, why GPUs can't be used for something, the data transfer takes so long, that it's better to make the calculation on the CPU.

Anyway, even if it would work, there would be probably just few, who would actually use it. Than better try to use GPUs at least as co-processors.

---

.

I think is more simple to introduce support to AVX/AVX2 extension than rewrite large part of the code to support GPU (or FPGA).

---